Announcements | Centre for Modeling and Simulation | Savitribai Phule Pune University

Colloquium | Parameterized Modeling and Model Order Reduction for Large Systems

Title	Parameterized Modeling and Model Order Reduction for Large Systems [slides]
Speaker	Elizabeth Rita Samuel, Surrogate Modeling Lab, Ghent University, Belgium Dr. Elizabeth Rita Samuel holds a Ph.D. in electrical engineering from Ghent University, Belgium. Her research work is showcased in many places, including here, here, and here.
Date & Time	Monday, 31 August 2015 \| 11:00-12:00
Venue	Kelkar Laboratory Centre for Modeling and Simulation, Savitribai Phule Pune University
Abstract	Design techniques are increasingly elaborate and innovative with the decreasing size and increasing complexity of today's integrated circuits. Also with the ongoing trend of increasing the speed of operations, it is important to take into account the interaction between the circuit and its surroundings, thereby necessitating accurate circuit simulation methods. One way to address this issue is through the use of faster hardware. However, at times the difficulty may not only be related to the size of the circuit but also to the time needed for the simulations, or to the model complexity involved. Thus, to improve the efficiency of the simulation process it is important to exploit the characteristic features of the particular problem using some algorithm or technique. One way to do this is by using model order reduction techniques. It captures the essential feature of a circuit and provides a simplified dynamical model for it. This yields efficient computation and storage capacity with reliable accuracy. Model order reduction performs order reduction only with respect to time or frequency. However, during the circuit design synthesis of large scale systems, it is also essential to analyse the response of a circuit as a function of design parameters, such as environmental effects, thermal effects, manufacturing variations and fluctuations in the critical dimension of geometrical layout features. A typical design procedure includes optimization and design space exploration, and thus requires repeated simulations for different design parameter values. Often it is not possible to perform multiple simulations of large circuits, due to the high computational cost per simulation. These design activities call for the development of parameterization techniques. Mainly interpolation based parameterized model order reduction techniques allow the use of various types of parameters, such as layout, geometrical and physical features.
Organizer/Host	Centre for Modeling and Simulation, Savitribai Phule Pune University

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